1. Field of the Invention
The present invention relates to an imaging apparatus that can achieve serial transfer of image signals produced by an imaging element by using a number of transfer channels, the number according with an operating mode.
2. Description of the Related Art
In recent years, the imaging apparatus can photograph more and more images in series, thanks to the increasing operating speed of the imaging element the imaging apparatus has. Along with this trend, the pixel rate of the image signals output from the imaging elements is increasing. Therefore, the image signals must be processed at high speed.
A technique is known, which may be used to cope with the increased pixel rate of image signals. This technique uses a low-voltage differential signaling (LVDS) system to accomplish serial transfer of image signals output from an imaging element. If the image signals are transferred by means of the LVDS system, the signals can be transferred at high speed and the energy required for their transfer can be reduced.
Imaging apparatuses developed in recent years incorporate imaging elements having a plurality of output channels. The image signals produced by such an imaging element can be output through these output channels concurrently. Further, an imaging apparatus has been proposed in which the number of channels used to output the image signals and the bit length of the image signals to transfer can be set in accordance with the operating mode of the imaging apparatus.
For example, in the imaging apparatus proposed in Jpn. Pat. Appln. KOKAI Publication No. 2008-283331, the sensor part (imaging element) provided in the imaging unit selects W operating channels in accordance with the operating mode. From each channel selected, an image signal having bit length n is output. These image signals are converted to differential serial image signals in the data transmission unit. The image signals, thus converted to serial signals, are supplied by means of serial transfer, through the W signal lines to the data reception unit provided in the image processing unit. A high-speed clock signal synchronous with the serial signals is output to the PLL incorporated in the image processing unit.
In the data reception unit, the serial signals corresponding to the operating channels, respectively, are converted to parallel signals having bit width M. The sync code embedded in each parallel signal is detected in the data restoration unit. From the sync code, a data window is extracted. From the data window, an image signal having bit length n is restored. The image signal restored is output to the signal processing unit. In the PLL, operating clock signals for use in the data reception unit, data restoration unit and clock gating circuit, respectively, are generated from the clock signal input as differential signals from the imaging unit.
The clock signal is output from the clock gating circuit to the signal processing circuit, only in a period in which the image signal restored in the data restoration unit remains valid. In the signal processing unit, the image signal is processed, only in a period in which the image signal, for which a clock signal is input from the clock gating circuit, remains valid. Signal processing is thus performed in the signal processing unit, in synchronism with the image signal.
Assume that the number of output channels that the imaging element has and the bit length of the image signal can be changed in accordance with the operating mode of the imaging apparatus. Then, the amount of data input, as image signal, from the imaging element changes in accordance with the operating mode. In this case, the clock signal to be synchronized with the image signals serially transferred must be changed, also in accordance with the operating mode. In the imaging apparatus of Jpn. Pat. Appln. KOKAI Publication No. 2008-283331, the high-speed clock signal input from the data transmission unit is converted to a clock signal of such a frequency band that the image processing unit can process it. This clock signal is used as operating clock signal, driving the clock gating circuit so that the signal processing unit may process signals in the imaging apparatus of Jpn. Pat. Appln. KOKAI Publication No. 2008-283331.